Electronics and Communication

 International Technical Championship-(ITC-2018) Respected Sathish Sir, On behalf of  IIT,Delhi  as the host, it gives us great pleasure to introduce a international level workshop series based on Mobile Making Indian Technologies will bring students from all over the world together to participate in the celebration of knowledge and creative extravagance along with experts from the fields of academic as well as industry.  This time Mobile Making Workshop will be organised by IIT,Delhi in association with Indian Technology  Make your college a zonal center  We are looking for  College of National repute to host our 2 days workshop and competition at their college campus. If You wish to associate with us and want to make...

We are glad to inform you that the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal is organizing a National workshop on Research Trends in Signal and Image Processing (RTSIP- 2017) from 6 th  to 7 th  October 2017. This event is a part of  the Diamond Jubilee celebrations of our Institution.   The Brochure of the workshop & registration form is attached herewith.  Interested students may register for the workshop BROCHURE: Click here to download

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CN 2nd Assignment is between  9th Oct to 13th Oct 2017 . The guidelines for 2nd Assignment: 1. The syllabus is L15 to L27 in the course plan 2. Since it is open book test, only printed material is allowed. 3. No Mobile Phones and Laptops are allowed. CN 3rd Assignment is between  23rd Oct to 28th Oct 2017 . The guidelines for 3rd Assignment:     2 Marks for Presentation (PPT) (Duration is max:  10minutes )    2 Marks for Report    4 Marks for Results & Viva Questions.

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Please note that the second assignment will be based on interfacing 8051 with the following devices. 1. 4*4 Keyboard 2. LED and switches 3. 7-segment display 4. LCD display 5. Stepper motor and DC motor 6. DAC and ADC You will have to prepare to write programs for the above mentioned interfacing topics, which will be asked in the second assignment.

Find attached the file contains the  list of students who have not yet registered in SLcM . Because of this the students can not see their academic performance and also their parents will not be able to access their ward's performance. Kindly  register in SLcM at the earliest.  LIST: Click here to download

VLSI mini project final submission starts from  03-10-2017  ( Tuesday ) . Please read the guidelines given below and be prepared. MINI PROJECT EVALUATION GUIDELINES 1.        The report  should be submitted in IEEE transaction on VLSI format. (i)                   Synopsis submission on time: 02 marks (ii)                 Presentation of Idea: 03 marks, (iii)               Writing draft paper in IEEE format: 05 marks, (iv)               Working demonstration: 10 marks. 2.        Submission of mini-projects will be in their  regular lab  time as per the given dates. Batch Date Day Time ...

Dear students,         3 rd  Assignment evaluation last date is on 30 th  October. Since this Assignment is project work at least for one month, expect you to start the work immediately.   Idea of project topics can be collected from your section faculty / can come up with your idea. Give the Title of project work to your section faculty before  20/09/17  ( Wednesday ).   Same Title is not accepted, at least idea of implementation/work platform should be change.  If same project work is found among four sections then students will be called for discussion with respective section faculties.  During evaluation submit the brief report of the project work (2 to 4 pages hand written-- one/group). Report format is attached.    SYNOPSIS: click here to download

Please find attached the topics for the 3rd assignment and guidelines . I hope you have formed a group having 5 members. CR has to send the list of groups to the concerned Teacher. F or the 2nd Assignment : The topic of interest is Memory  and Memory management You have to study on all types of memory, cell structure, latest technologies in memory design, memory access types,  memory interface, memory management like segmentation, paging. ASSIGNMENT 3: click here to download

NOTICE: click here to download APPLICATION FORM: click here to download ROLES & RESPONSIBILITY: click here to download ELIGIBILITY CRITERIA & SCHEDULE: click here to download

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PROCEDURE: 3 rd  Assignment evaluation last date is on 30 th  October. Since this Assignment is project work at least for one month, expect you to start the work immediately.   Idea of project topics can be collected from your section faculty / can come up with your idea. Give the Title of project work to your section faculty before  20/09/17  ( Wednesday ).   Same Title is not accepted, at least idea of implementation/work platform should be change.  If same project work is found among four sections then students will be called for discussion with respective section faculties.  During evaluation submit the brief report of the project work (2 to 4 pages hand written-- one/group). Report format is attached.    PROJECT REPORT FORMAT: click here to download

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Below given are the topics for 2nd Assignment (i) channel length modulations, body-effect, threshold voltage ( PMOS and CMOS) (ii) Lithography  (iii) Flash Memory (iv) Sheet resistance  (v) Delay calculations in NMOS and CMOS. 

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NOTES: click here to download

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