VLSI LAB INSTRUCTIONS
Pre-lab Preparation
* Each lab experiment requires the preparation that may involve a significant amount of work.
* The pre-lab work must be completed before arrival at the lab. The pre-lab work will be part of your lab grade and will be evaluated every week.
* The student must revise concepts related to Logic design and Verilog Programming before coming to VLSI Lab.
Lab Journal
The students have to maintain Lab Journals and need to submit the same to the faculty at the start of each lab. Each experiment must be written neatly and include the following details as applicable
* Experiment Number and Date
* Experiment Title and Objective
* Verilog constructs used
* Truth table, Logic equation and circuit diagram for combinational circuits (exercise problems only)
* State diagram/ state table and circuit diagram for sequential circuits ( exercise problems only)
* Verilog code for each exercise problem.
* Simulation results and analysis
* Conclusion(s)
* Solution to additional assignment problems if any given by faculty
Daily Evaluation
* Maintain neat lab journal: 03 Marks
* Conduction (solved examples) and complete involvement in the lab: 04 Marks
* Conduction of exercise problems:03 Marks
Mini Project
*The student has to submit their synopsis of the mini project during 21-26 August. The student is allowed to make a group of two members. Repetition of the same project in the same batch is strictly prohibited. The date of submission of their project submission and evaluation will be intimated later.
Regarding Missing labs
1 .The student is not allowed to miss more than two labs. For two labs, absence with the valid reason they will be evaluated out of 10 otherwise 6 Marks. For rest absence (if the students miss more than two lab sessions) 0 marks will be awarded. In either of the case, the students must repeat the experiments which they have missed. If the students have not repeated or completed all the experiments, they will be detained and will not be eligible for the lab end exam.
2. To repeat the lab student should get prior permission by writing the letter and getting approved through lab coordinators with supporting documents
* Each lab experiment requires the preparation that may involve a significant amount of work.
* The pre-lab work must be completed before arrival at the lab. The pre-lab work will be part of your lab grade and will be evaluated every week.
* The student must revise concepts related to Logic design and Verilog Programming before coming to VLSI Lab.
Lab Journal
The students have to maintain Lab Journals and need to submit the same to the faculty at the start of each lab. Each experiment must be written neatly and include the following details as applicable
* Experiment Number and Date
* Experiment Title and Objective
* Verilog constructs used
* Truth table, Logic equation and circuit diagram for combinational circuits (exercise problems only)
* State diagram/ state table and circuit diagram for sequential circuits ( exercise problems only)
* Verilog code for each exercise problem.
* Simulation results and analysis
* Conclusion(s)
* Solution to additional assignment problems if any given by faculty
Daily Evaluation
* Maintain neat lab journal: 03 Marks
* Conduction (solved examples) and complete involvement in the lab: 04 Marks
* Conduction of exercise problems:03 Marks
Mini Project
*The student has to submit their synopsis of the mini project during 21-26 August. The student is allowed to make a group of two members. Repetition of the same project in the same batch is strictly prohibited. The date of submission of their project submission and evaluation will be intimated later.
Regarding Missing labs
1 .The student is not allowed to miss more than two labs. For two labs, absence with the valid reason they will be evaluated out of 10 otherwise 6 Marks. For rest absence (if the students miss more than two lab sessions) 0 marks will be awarded. In either of the case, the students must repeat the experiments which they have missed. If the students have not repeated or completed all the experiments, they will be detained and will not be eligible for the lab end exam.
2. To repeat the lab student should get prior permission by writing the letter and getting approved through lab coordinators with supporting documents
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